1. Field of Invention
Embodiments of the present invention relate to methods of forming a diode and methods of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) using the same. More particularly, embodiments of the present invention relate to a method of forming a vertical diode in which a polysilicon layer may be formed at a relatively low temperature, and a method of manufacturing a semiconductor device using the same.
2. Description of the Related Art
Generally, semiconductor memory devices can be classified as either volatile semiconductor memory devices or non-volatile semiconductor memory devices. Volatile semiconductor memory devices include dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices. Non-volatile semiconductor memory devices include flash memory devices and electrically erasable programmable read-only memory (EEPROM) devices. Flash memory devices are widely incorporated within electrical devices such as digital cameras, cellular phones, MPEG audio 3 players (MP3), etc. However, it may take a relatively long time to input/output data into/from a flash memory device. Accordingly, flash memory devices have been recently replaced with next generation semiconductor memory devices such as magnetoresistive random access memory (MRAM) devices, ferroelectric random access memory (FRAM) devices, phase-change random access memory (PRAM) devices, etc.
In a PRAM device, data may be input or output using a resistance difference between an amorphous state and a crystalline state of a phase-change material layer including a chalcogenide material, which may be generated by a phase transition of the phase-change material layer. For example, data having a value of “0” or “1” may be stored in the PRAM device using a reversible phase transition of the phase-change material layer in accordance with a width and a length of pulse applied thereto. The phase-change material layer may include a chalcogenide material such as germanium-antimony-tellurium (Ge—Sb—Te, GST). When a reset/set current is applied to a PRAM device, the reset/set current flows from a transistor through a lower electrode to a phase-change material layer. As a result, a phase transition may be generated in the phase-change material layer. The reset current changes the phase of the phase-change material layer from a crystalline state into an amorphous state while the set current changes the phase of the phase-change material layer from the amorphous state into the crystalline state. The phase-change material layer in the crystalline state may have a resistance lower than that of the phase-change material layer in the amorphous state.
Generally, a PRAM device includes a switching element connected to a word line, a lower electrode, an upper electrode and a phase-change material layer disposed between the lower electrode and the upper electrode. Usually, a transistor serves as the switching element. However, when the transistor is used as the switching element, the transistor may not have a driving current capacity greater than about 1 mA, which is required for a phase-transition of the phase-change material layer. Thus, research has been conducted to develop a vertical diode suitable for use as the switching element to replace the transistor. The vertical diode may be formed by implanting n-type impurities or p-type impurities into a polysilicon layer. For example, the vertical diode is formed by implanting n-type impurities into a lower portion of the polysilicon layer and p-type impurities into an upper portion thereof.
A selective epitaxial growth (SEG) process is generally performed in order to form a polysilicon layer. In the SEG process, after forming an insulation layer on a substrate, the insulation layer is partially removed to form an insulation layer pattern which has an opening therethrough exposing an active region of the substrate. The polysilicon layer is formed on the substrate using the exposed active region as a seed.
However, when the insulation layer is patterned to form the insulation layer pattern having the opening, the active region exposed by the opening may be damaged. Additionally, when the insulation layer has a multilayer structure in which different layers are stacked, an interface stress may be generated between adjacent layers in the multilayer structure. Due to the damage to the active region or the interface stress, it may not be easy to form a polysilicon layer having a gross grain size.
The polysilicon layer may be transformed from an amorphous silicon layer by performing a heat treatment process after forming the amorphous silicon layer in the opening. The amorphous silicon layer may be crystallized by the heat treatment process. However, the heat treatment process is usually performed at a temperature higher than about 600° C. As a result, the crystalline characteristics of the polysilicon layer may be inferior compared to the crystalline characteristics of a polysilicon layer formed by the SEG process. Thus, the polysilicon layer formed by the heat treatment process may have a relatively high internal resistance, and a driving current of about 1 mA may not flow through the polysilicon layer.